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Cadence RF Design Methodology Kit
The Cadence RF Design Methodology Kit helps shorten product development cycle time by increasing silicon predictability and enabling greater RF design productivity. It demonstrates advanced methodologies for intelligently managing RLCK parasitics, inductance synthesis and modeling, and linking system-level design with IC design. The kit also comprises methodologies that enable designers to accurately, yet rapidly verify complete designs that include system-level digital, analog base-band, and RF circuitry.
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Cadence Optimization Methodology Kit for ARM Processors
The Cadence® Optimization Methodology Kit for ARM Processors massively simplifies the implementation techniques used to achieve higher performance, lower power and less area (PPA) for ARM-based designs. The kit couples expert service and support with industry-leading Cadence Encounter RTL Compiler global synthesis, First Encounter virtual prototyping and ARM's Artisan/TSMC 0.13m SageX and TSMC 90G libraries. With this package, customers can achieve specified PPA levels and substantial reductions in development time required for hardening ARM processor cores. The Cadence Optimization Methodology Kit for ARM Processors has been designed to provide significant low power optimization enhancements to the ARM-Cadence Reference Methodology.
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Cadence AMS Methodology Kit
The Cadence® AMS Methodology Kit addresses analog/mixed-signal design challenges across some of today's most competitive markets, including wireless, wired networking, and personal entertainment electronics. The Kit delivers a verified methodology, enabling IP, and consulting, all of which is demonstrated on an end-to-end mixed-signal design example.
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Cadence functional Verification Kit for ARM
Jointly developed by Cadence and ARM, the Cadence® Functional Verification Kit for ARM offers a comprehensive verification solution specifically for engineers developing ARM® processor-based designs. The Kit contains ARM processor-based verification methodology and flows, a reference design platform, verification process automation (VPA) technology, and reusable verification IP. The proven Incisive® Plan-to-Closure Methodology from Cadence has been tailored specifically to ARM processor-based designs.
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Cadence RF SiP Design Methodology Kit
The Cadence® RF SiP Methodology Kit accelerates the application of advanced EDA technologies to system-in-package (SiP) designs for Radio Frequency (RF)/wireless applications. It provides methodologies that maximize design productivity and predictability for customers leveraging the advantages of SiP implementation. An integrated set of SiP design products built around proven methodologies—demonstrated on a segment representative design—enables complete front-to-back SiP design and implementation.
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