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STMicroelectronics and Synopsys Demonstrate Interoperability of Their SATA IP Cores for 90nm Technology
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Synopsys Announces Industry's First Wireless USB Device Controller IP Based on the Certified Wireless USB Specification
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Synopsys IC Compiler In ARM-Synopsys Reference Methodology
ARM and Synopsys have confirmed the availability of ARM-Synopsys Galaxy Reference Methodology for streamlining high-performance implementations of synthesizable ARM processors. This enhanced RM incorporates IC Compiler, Synopsys' next-generation physical design system, to more easily achieve higher clock frequencies compared to earlier versions of the RM.
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Synopsys DesignWare IP to Enable Next-Generation PCI Express 2.0 Products
Synopsys Is First to Deliver PCI Express Gen II Digital IP for Increased Bandwidth in Networking, Embedded and Computer Applications
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Synopsys to Highlight Complete Wireless USB, PCI Express, SATA and Mobile Storage IP Solutions at Intel Developers' Forum 2006
Synopsys, a world leader in semiconductor design software, will highlight its complete wireless USB, PCI Express®, SATA and Mobile Storage IP solutions at the Intel Developers' Forum in San Francisco, California on March 7, 2006. Synopsys is the leader in connectivity IP offering a complete solution of digital, PHY and verification IP.
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Synopsys' New DesignWare Bridge IP for PCI Express to AMBA 3 AXI Connects Two High-Performance Domains
Synopsys, a world leader in semiconductor design software, announced the availability of the DesignWare(R) Bridge Intellectual Property (IP) for PCI Express(R) to AMBA(R) 3 AXI(TM) protocol. The bridge to AMBA 3 AXI protocol is used in conjunction with Synopsys' complete portfolio of DesignWare IP for PCI Express version 1.1 and preliminary 2.0 (Gen II), including Endpoint, Root Complex, Switch, Bridge and Dual Mode. Designers who are using the high-performance serial PCI Express interface to interconnect their system-on-chip (SoC) designs in networking, embedded, storage and computer applications have begun migrating their standard on-chip bus to the AMBA 3 AXI protocol to preserve the full bus bandwidth. By providing a PCI Express to AMBA 3 AXI bridge, Synopsys is enabling designers who use the AMBA 3 AXI protocol to easily add PCI Express external connectivity to their SoCs.
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Synopsys Continues IC Compiler Momentum With 2006.06 Release
Synopsys, a world leader in semiconductor design software, announced the 2006.06 release of IC Compiler, Synopsys' next-generation place- and-route solution. The 2006.06 release delivers advances in the areas of integrated design planning, enhanced physical test, advanced low-power design, true concurrent multi-corner/multi-mode optimization, and design-for-yield techniques. This release continues the momentum initiated by the introduction of the IC Compiler solution in June 2005. Since then, IC Compiler has steadily drawn customers from a broad class of applications, from cost-conscious 180- and 130-nanometer (nm) designs to performance-driven 65-nm designs. Several of these prominent customers are scheduled to detail their tapeout experiences using IC Compiler at the Design Automation Conference in San Francisco next month.
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Synopsys and First Silicon Solutions Speed Development of Large PCI Express Designs
Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, and First Silicon Solutions (FS2), a division of MIPS Technologies, Inc. (Nasdaq: MIPS) and a leader in on-chip instrumentation intellectual property (IP) for high-performance debug solutions, announced the availability of the Sitka evaluation and development platform for Synopsys' DesignWare(R) PCI Express(R) (PCIe) IP. The Sitka Board, the result of collaboration between the two companies, functions as a standard PCIe add-in card with support for up to eight PCIe lanes (each lane is a 2.5 Gbps communication channel). With this new platform, designers can test and debug their system-on-chip (SoC) designs using the DesignWare PCIe IP while performing interoperability testing between their SoC design and a PCIe PHY. Designers using the Sitka board to prototype SoCs can reduce their design risk, cut development time and enable predictable success in their complex SoCs.
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