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Altera HardCopy II Structured ASICs
HardCopy® II structured ASICs are the industry's most compelling structured ASICs. The only structured ASICs to feature a unique FPGA front-end design methodology, HardCopy II devices deliver the lowest-risk, fastest time-to-market solution in the industry. Test your designs with Stratix® II FPGA prototypes, then Altera’s HardCopy Design Center seamlessly migrates the designs to a low-cost, functionally equivalent, pin-compatible HardCopy II device.
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Altera MAX II CPLD
Altera introduces the MAX® II device family, the lowest-cost CPLDs ever. MAX II devices are based on a groundbreaking new CPLD architecture that delivers the lowest cost per I/O pin and the lowest power of any CPLD family. Featuring a low-power process technology, MAX II devices deliver half the cost, one-tenth the power, four times the density, and twice the performance of previous MAX devices.
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Altera Stratix II GX FPGA
The Stratix® II GX family is Altera's third generation of FPGAs with embedded transceivers. The family has been architected to provide a robust solution for the growing number of applications and protocols requiring high-speed serial I/O. Stratix II GX FPGAs are built using the industry’s fastest and highest-density Stratix II FPGA fabric and integrate up to 20 serializer/deserializer (SERDES)-based transceivers.
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Altera Stratix II FPGA
FPGA density and performance reaches new heights with the Stratix® II device family – the industry’s biggest and fastest FPGAs. Built on a new and innovative logic structure, Stratix II devices deliver on average 50 percent higher performance and offer more than twice the logic capacity than the award-winning first-generation Stratix FPGAs. Benchmarking results show that Stratix II FPGAs deliver the highest performance and density of any competing FPGAs. Stratix II devices support internal clock frequency rates of up to 500 MHz and typical design performance at over 250 MHz. The Stratix II logic structure allows designers to pack significantly more functionality into less area, further reducing product costs. Designers can get ASIC-like density and performance with the time-to-market advantages of programmable logic. In addition, Stratix II devices are also well suited for ASIC prototyping.
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PLDApplications
High-speed connectivity IP Cores & Boards for ASIC, ASSP & FPGA Designers, including PCI Express IP Core ; PCI-X IP Core ; PCI IP Core ; AHB-PCI Bridge IP Core.
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Altera Cyclone II FPGAs
Following Altera's immensely successful first-generation Cyclone family, Cyclone II FPGAs were built from the ground up for low cost and provide a customer-defined feature set for high-volume solutions to cost-sensitive applications. Cyclone II devices are manufactured on 300-mm wafers using TSMC’s 90-nm low-k dielectric process to deliver high performance and low power consumption at a cost that rivals that of ASICs. Cyclone II FPGAs are supported by the easy to use and free Quartus® II Web Edition design software, a broad catalog of intellectual property (IP), and hardware development kits to enable rapid development of low-cost FPGA solutions.
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